MC68HC908AT32 Datasheet, PDF (277/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
23.13.8 MSCAN08 Transmitter Control Register
Address:
Read:
Write:
Reset:
$0507
Bit 7
6
5
4
3
0
0
ABTRQ2 ABTRQ1 ABTRQ0
2
TXEIE2
1
TXEIE1
0
0
0
0
0
0
0
= Unimplemented
Figure 23-21. Transmitter Control Register (CTCR)
Bit 0
TXEIE0
0
ABTRQ2–ABTRQ0 — Abort Request Flag
The CPU sets this flag to request that an already scheduled message buffer (TXE = 0) be aborted. The
MSCAN08 will grant the request when the message is not already under transmission. When a
message is aborted, the associated TXE and the abort acknowledge flag (ABTAK) (see 23.13.7
MSCAN08 Transmitter Flag Register) will be set and an TXE interrupt will occur if enabled. The CPU
cannot reset this flag. The flag is reset implicitely whenever the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable Bits
1 = A transmitter empty (transmit buffer available for transmission) event will result in a transmitter
empty interrupt.
0 = No interrupt will be generated from this event.
23.13.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
0
IDAM1 IDAM0
0
IDHIT1 IDHIT0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 23-22. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode Flags
The CPU sets these flags to define the identifier acceptance filter organization (see 23.5 Identifier
Acceptance Filter). Table 23-8 summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 23-8. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Single 32-bit acceptance filter
Two 16-bit acceptance filter
Four 8-bit acceptance filters
Filter closed
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
277