MC68HC908AT32 Datasheet, PDF (363/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
29.7 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
Num⁽¹⁾
Characteristic⁽²⁾
Symbol
Min
Max
Unit
Operating frequency⁽³⁾
Master
Slave
f_BUS(M)
f_Bus(S)
f_BUS/128
dc
f_BUS/2
f_BUS
MHz
Cycle time
1
Master
Slave
t_cyc(M)
t_cyc(S)
2
128
t_cyc
1
—
2
Enable lead time
t_Lead
15
—
ns
3
Enable lag time
t_Lag
15
—
ns
Clock (SCK) high time
4
Master
Slave
t_W(SCKH)M
100
t_W(SCKH)S
50
—
ns
—
Clock (SCK) low time
5
Master
Slave
t_W(SCKL)M
100
t_W(SCKL)S
50
—
ns
—
Data setup time (inputs)
6
Master
Slave
t_SU(M)
t_SU(S)
45
—
ns
5
—
Data hold time (inputs)
7
Master
Slave
t_H(M)
t_H(S)
0
—
ns
15
—
Access time, slave⁽⁴⁾
8
CPHA = 0
CPHA = 1
t_A(CP0)
t_A(CP1)
0
40
ns
0
20
9
Slave disable time (hold time to high-impedance state)⁽⁵⁾
t_DIS
—
25
ns
Data valid time after enable edge⁽⁶⁾
10
Master
Slave
t_V(M)
t_V(S)
—
10
ns
—
40
Data hold time (outputs, after enable edge)
11
Master
Slave
t_HO(M)
t_HO(S)
0
—
ns
5
—
1. Item numbers refer to dimensions in Figure 29-1 and Figure 29-2.
2. All timing is shown with respect to 30% V_DD and 70% V_DD, unless otherwise noted; assumes 100 pF load on all SPI pins.
3. f_Bus = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. Hold time to high-impedance state.
6. With 100 pF on all SPI pins
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
363