MC68HC908AT32 Datasheet, PDF (104/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive
CGMOUT. When BCS is clear, XLD always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure software portability from
development systems to user applications, software should write 0s to bits 3–0 when writing to PBWC.
8.5.3 PLL Programming Register
The PLL programming register contains the programming information for the modulo feedback divider
and the programming information for the hardware configuration of the VCO.
Address:
Read:
Write:
Reset:
$001E
Bit 7
6
5
4
3
2
1
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
0
1
1
0
0
1
1
Figure 8-6. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier,
N. (See 8.3.2.1 Circuits and 8.3.2.4 Programming the PLL.) A value of $0 in the multiplier select bits
configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to
give a default multiply value of 6. See Table 8-2.
NOTE
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
Table 8-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L, which controls the
hardware center-of-range frequency, f_VRS. (See 8.3.2.1 Circuits, 8.3.2.4 Programming the PLL, and
8.5.1 PLL Control Register.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control
register (PCTL) is set. See 8.3.2.5 Special Programming Exceptions. A value of $0 in the VCO range
MC68HC908AT32 Data Sheet, Rev. 3.1
104
Freescale Semiconductor