MC68HC908AT32 Datasheet, PDF (137/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRQ Status and Control Register
15.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
• Shows the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt request
• Controls triggering sensitivity of the IRQ1/V_PP interrupt pin
Address:
Read:
Write:
Reset:
$001A
Bit 7
6
5
0
0
0
R
R
R
0
0
0
R
= Reserved
4
3
2
1
0
IRQF1
0
IMASK1
R
R
ACK1
0
0
0
0
Figure 15-4. IRQ Status and Control Register (ISCR)
Bit 0
MODE1
0
IRQ1F — IRQ1 Flag Bit
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic 0. Reset clears
ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1/V_PP pin. Reset clears MODE1.
1 = IRQ1/V_PP interrupt requests on falling edges and low levels
0 = IRQ1/V_PP interrupt requests on falling edges only
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
137