MC68HC908AT32 Datasheet, PDF (134/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
ACK1
VECTOR
FETCH
DECODER
IRQ1/V_PP
V_DD
D ^CLR Q
CK
IRQ1
LATCH
SYNCHRO-
NIZER
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
Figure 15-1. IRQ Block Diagram
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ1F
IRQ1
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
Addr.
$001A
Register Name
Bit 7
6
5
4
3
IRQ Status and Control Register ^{Read: 0}
0
0
0
IRQF1
(ISCR) Write: R
R
R
R
R
See page 137. _{Reset: 0}
0
0
0
0
R = Reserved
Figure 15-2. IRQ I/O Register Summary
2
0
ACK1
0
1
Bit 0
IMASK1 MODE1
0
0
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 15-3.)
MC68HC908AT32 Data Sheet, Rev. 3.1
134
Freescale Semiconductor