MC68HC908AT32 Datasheet, PDF (369/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

29.14 BDLC Receiver VPW Symbol Timings
BDLC Receiver VPW Symbol Timings
Characteristic⁽¹⁾
Number
Symbol⁽²⁾
Min
Typ
Max
Unit
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start-of-frame (SOF)
End-of-data (EOD)
End-of-frame (EOF)
Break
10
t_TRVP1
34
64
96
µs
11
t_TRVP2
96
128
163
µs
12
t_TRVA1
96
128
163
µs
13
t_TRVA2
34
64
96
µs
14
t_TRVA3
163
200
239
µs
15
t_TRVP3
163
200
239
µs
16
t_TRV4
239
280
320
µs
18
t_TRV6
280
—
—
µs
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V.
2. The transmitter symbol timing boundaries are subject to an uncertainty of 1 t_BDLC µs due to sampling considerations.
14
10
12
SOF
13
11
0
0
15
1
1
0
EOD
16
EOF
18
BRK
Figure 29-3. BDLC Variable Pulse-Width Modulation (VPW) Symbol Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
369