MC68HC908AT32 Datasheet, PDF (256/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
• Quadruple identifier acceptance filter to be applied to the first eight bits of the identifier. This mode
implements four independent filters for the first eight bits of a CAN 2.0A compliant standard
identifier.
The identifier acceptance registers (CIAR) define the acceptable pattern of the standard or extended
identifier (ID10–ID0 or ID28–ID0). Any of these bits can be marked don’t care in the identifier mask
register (CIMR).
ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2
ID7 ID6
IDR3 RTR
ID10 IDR0
ID3 ID2
IDR1 IDE ID10 IDR2
ID3 ID10 IDR3
ID3
AC7 CIDMR0 AC0 AC7 CIDMR1 AC0 AC7 CIDMR2 AC0 AC7 CIDMR3 AC0
AC7 CIDAR0 AC0 AC7 CIDAR1 AC0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0
ID ACCEPTED (FILTER 0 HIT)
Figure 23-3. Single 32-Bit Maskable Identifier Acceptance Filter
The background buffer, RxBG, will be copied into the foreground buffer, RxFG, and the RxF flag will be
set only in case of an accepted identifier (an identifier acceptance filter hit). A hit also will cause a receiver
interrupt if enabled.
ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2
ID10 IDR0
ID3 ID2
IDR1 IDE ID10 IDR2
ID7 ID6
IDR3 RTR
ID3 ID10 IDR3
ID3
AC7 CIDMR0 AC0 AC7 CIDMR1 AC0
AC7 CIDAR0 AC0 AC7 CIDAR1 AC0
ID ACCEPTED (FILTER 0 HIT)
AC7 CIDMR2 AC0 AC7 CIDMR3 AC0
AC7 CIDAR2 AC0 AC7 CIDAR3 AC0
ID ACCEPTED (FILTER 1 HIT)
Figure 23-4. Dual 16-Bit Maskable Acceptance Filters
MC68HC908AT32 Data Sheet, Rev. 3.1
256
Freescale Semiconductor