MC68HC908AT32 Datasheet, PDF (213/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs
as the input to the TIMB counter as Table 19-1 shows. Reset clears the PS[2:0] bits.
PS[2:0]
000
001
010
011
100
101
110
111
Table 19-1. Prescaler Selection
TIMB Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTD6/ATD14/TACLK
19.8.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
Register Name and Address: TBCNTH — $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Register Name and Address: TBCNTL — $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-5. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
213