EP4CE30F29C7N Datasheet, PDF (95/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Cascading
5–33
Figure 5–21 shows an example of phase shift insertion using fine resolution through
VCO phase taps method. The eight phases from the VCO are shown and labeled for
reference. In this example, CLK0 is based on 0° phase from the VCO and has the C
value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and has the C value for the counter set to one. The CLK1 signal is also
divided by four. In this case, the two clocks are offset by 3 Φ_fine. CLK2 is based on the
0° phase from the VCO but has the C value for the counter set to three. This creates a
delay of two Φ_coarse (two complete VCO periods).
Figure 5–21. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 t_VCO
t_VCO
0
45
90
135
180
225
270
315
CLK0
CLK1
CLK2
t_d0-1
t_d0-2
You can use the coarse and fine phase shifts to implement clock delays in
Cyclone IV devices.
Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The
phase shift is configurable for any number of times. Each phase shift takes about one
scanclk cycle, allowing you to implement large phase shifts quickly.
PLL Cascading
Cyclone IV devices allow cascading between general purpose PLLs and multipurpose
PLLs in normal or direct mode through the GCLK network. If your design cascades
PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the
destination (downstream) PLL must have a high-bandwidth setting.
1 PLL_6 and PLL7 have upstream cascading capability only.
1 PLL cascading is not supported when used in transceiver applications.
October 2012 Altera Corporation
Cyclone IV Device Handbook,
Volume 1