EP4CE30F29C7N Datasheet, PDF (109/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 6: I/O Features in Cyclone IV Devices
6–3
I/O Element Features
Figure 6–1 shows the Cyclone IV devices IOE structure for single data rate (SDR)
operation.
Figure 6–1. Cyclone IV IOEs in a Bidirectional I/O Configuration for SDR Mode
io_clk[5..0]
Column
or Row
Interconnect
OE
clkout
oe_out
aclr/prn
Chip-Wide Reset
data_in1
data_in0
sclr/
preset
clkin
oe_in
OE Register
D
Q
ENA
ACLR
/PRN
V_CCIO
Optional
PCI Clamp
V_CCIO
Programmable
Pull-Up
Resistor
Output Register
Output
(1)
Pin Delay
D
Q
ENA
ACLR
/PRN
Current Strength Control
Open-Drain Out
Slew Rate Control
D
Q
ENA
ACLR
/PRN
Input Register
Input Pin to
Input Register
Delay
or Input Pin to
Logic Array
Delay
Bus Hold
Note to Figure 6–1:
(1) Tri-state control is not available for outputs configured with true differential I/O standards.
I/O Element Features
The Cyclone IV IOE offers a range of programmable features for an I/O pin. These
features increase the flexibility of I/O utilization and provide a way to reduce the
usage of external discrete components, such as pull-up resistors and diodes.
Programmable Current Strength
The output buffer for each Cyclone IV I/O pin has a programmable current strength
control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I
and II, HSTL-15 Class I and II, and HSTL-12 Class I and II I/O standards have several
levels of current strength that you can control.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1