EP4CE30F29C7N Datasheet, PDF (310/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–30
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
The CDR unit in each receiver channel gets the CDR clocks from one of the two
multipurpose PLLs directly adjacent to the transceiver block. The CDR clocks
distribution network is segmented by bidirectional tri-state buffers as shown in
Figure 1–29 and Figure 1–30. This requires the CDR clocks from either one of the two
multipurpose PLLs to drive a number of contiguous segmented paths to reach the
intended receiver channel. Interleaving the CDR clocks from the two multipurpose
PLLs is not supported.
For example, based on Figure 1–29, a combination of MPLL_1 driving receiver channels
0, 1, and 3, while MPLL_2 driving receiver channel 2 is not supported. In this case, only
one multipurpose PLL can be used for the receiver channels.
Figure 1–29. CDR Clocking for Transceiver Channels in F324 and Smaller Packages
MPLL_2
Ch3
(1) ^CDR
Ch2
Transceiver (1) ^CDR
Block
GXBL0 ^Ch1 CDR
Ch0 CDR
CDR
clocks
MPLL_1
Note to Figure 1–29:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
Figure 1–30. CDR Clocking for Transceiver Channels in F484 and Larger Packages
MPLL_8
Ch3 _CDR
Transceiver ^{Ch2 CDR}
Block
GXBL1 ^Ch1 CDR
Ch0 CDR
MPLL_7
MPLL_6
Ch3 CDR
Transceiver ^{Ch2 CDR}
Block
GXBL0 ^Ch1 CDR
Ch0 CDR
MPLL_5
CDR
clocks
Not applicable in
F484 package
CDR
clocks
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation