EP4CE30F29C7N Datasheet, PDF (320/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–40
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
When the byte serializer is enabled, the common bonded low-speed clock frequency is
halved before feeding to the read clock of TX phase compensation FIFO. The common
bonded low-speed clock is available in FPGA fabric as coreclkout port, which can be
used in FPGA fabric to send transmitter data and control signals to the bonded
channels.
Figure 1–38. Transmitter Only Datapath Clocking in Bonded Channel Configuration
FPGA
Fabric
tx_coreclk[3]
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS 3
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Transmitter Channel PCS 2
Transmitter Channel PMA 3
Serializer
high-speed
clock
Transmitter Channel PMA 2
tx_coreclk[2]
coreclkout
Tx Phase
Comp
FIFO
wr_clk rd_clk
/2
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Transmitter Channel PCS 1
Serializer
high-speed
clock
Transmitter Channel PMA 1
tx_coreclk[1]
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Transmitter Channel PCS 0
Serializer
high-speed
clock
low-speed clock
Transmitter Channel PMA 0
tx_coreclk[0]
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
/2
8B/10B Encoder
Serializer
high-speed
clock
In +2 Bonded Channel Configuration
In +4 Bonded Channel Configuration
1 Bonded channel configuration is not available for Receiver Only channel operation
because each of the channels are individually clocked by its recovered clock.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation