EP4CE30F29C7N Datasheet, PDF (309/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
1–29
Figure 1–27 shows an example of the termination scheme for AC-coupled connections
for REFCLK pins.
Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock
LVDS, LVPECL, PCML
(1.2 V, 1.5 V, 3.3 V)
0.1 μF
0.1 μF
Z₀ = 50 Ω
Z₀ = 50 Ω
V_ICM
50 Ω
50 Ω
Cyclone IV GX
REFCLK
Note to Figure 1–27:
(1) For more information about the V_ICM value, refer to the Cyclone IV Device Datasheet chapter.
Figure 1–28 shows an example termination scheme for the REFCLK pin when
configured as a HCSL input.
Figure 1–28. Termination Scheme for a Reference Clock When Configured as HCSL ⁽¹⁾
PCI Express
(HCSL)
REFCLK
Source
Rs (2)
Rs (2)
Cyclone IV GX
REFCLK +
REFCLK -
50 Ω
50 Ω
Notes to Figure 1–28:
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
specification.
(2) Select values as recommended by the PCIe clock source vendor.
Transceiver Channel Datapath Clocking
Channel datapath clocking varies with channel configuration options and PCS
configurations. This section describes the clock distribution from the left PLLs for
transceiver channels and the datapath clocking in various supported configurations.
Table 1–7 lists the clocks generated by the PLLs for transceiver datapath.
Table 1–7. PLL Clocks for Transceiver Datapath
Clock
Usage
CDR clocks
High-speed clock
Low-speed clock
Receiver CDR unit
Transmitter serializer block in PMA
Transmitter PCS blocks
Receiver PCS blocks when rate match FIFO enabled
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2