EP4CE30F29C7N Datasheet, PDF (161/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Features
7–15
Figure 7–9 illustrates how the second output enable register extends the DQS
high-impedance state by half a clock cycle during a write operation.
Figure 7–9. Extending the OE Disable by Half a Clock Cycle for a Write Transaction ⁽¹⁾
System clock
(outclock for DQS)
OE for DQS
(from logic array)
90^o
DQS
Write Clock
(outclock for DQ,
-90^ophase shifted
from System Clock)
datain_h
(from logic array)
datain_I
(from logic array)
OE for DQ
(from logic array)
DQ
Delay
by Half
a Clock
Cycle
Preamble
Postamble
D0
D2
D1
D3
D0
D1
D2
D3
Note to Figure 7–9:
(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements the signal as an active high and automatically adds an inverter before the A_OE register
D input.
OCT with Calibration
Cyclone IV devices support calibrated on-chip series termination (R_S OCT) in both
vertical and horizontal I/O banks. To use the calibrated OCT, you must use the RUP
and RDN pins for each R_S OCT control block (one for each side). You can use each
OCT calibration block to calibrate one type of termination with the same V_CCIO for
that given side.
f For more information about the Cyclone IV devices OCT calibration block, refer to the
Cyclone IV Device I/O Features chapter.
PLL
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQS write signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQ signals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
1 The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories. PLL reconfiguration is used in the ALTMEMPHY megafunction to
calibrate and track the read-capture phase to maintain the optimum margin.
f For more information about usage of PLL outputs by the ALTMEMPHY
megafunction, refer to the External Memory Interface Handbook.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1