EP4CE30F29C7N Datasheet, PDF (313/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
1–33
Figure 1–31 and Figure 1–32 show the high- and low-speed clock distribution for
transceivers in F324 and smaller packages, and in F484 and larger packages in
non-bonded channel configuration.
Figure 1–31. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F324
and Smaller Packages
(2)
MPLL_2
(3)
Ch3 TX PMA
(1)
Ch2 TX PMA
Transceiver (1)
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
MPLL_1
Notes to Figure 1–31:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2