EP4CE30F29C7N Datasheet, PDF (132/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

6–26
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks
Differential I/O Standards
I/O Bank Location
External Resistor
Network at
Transmitter
Transmitter (TX)
Receiver (RX)
LVDS
5,6
Not Required
v
v
3,4,5,6,7,8
Three Resistors
5,6
Not Required
RSDS
3,4,7,8
Three Resistors
v
—
3,4,5,6,7,8
Single Resistor
mini-LVDS
5,6
Not Required
v
—
3,4,5,6,7,8
Three Resistors
PPDS
5,6
Not Required
v
—
3,4,5,6,7,8
Three Resistors
BLVDS ⁽¹⁾
3,4,5,6,7,8
Single Resistor
v
v
LVPECL ⁽²⁾
Differential SSTL-2 ⁽³⁾
3,4,5,6,7,8
—
—
v
3,4,5,6,7,8
—
v
v
Differential SSTL-18 ⁽³⁾
Differential HSTL-18 ⁽³⁾
3,4,5,6,7,8
—
v
v
3,4,5,6,7,8
—
v
v
Differential HSTL-15 ⁽³⁾
3,4,5,6,7,8
—
v
v
Differential HSTL-12 ⁽³⁾
4,5,6,7,8
—
v
v
Notes to Table 6–7:
(1) Transmitter and Receiver f_MAX depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
You can use I/O pins and internal logic to implement a high-speed differential
interface in Cyclone IV devices. Cyclone IV devices do not contain dedicated
serialization or deserialization circuitry. Therefore, shift registers, internal
phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel
conversions on incoming data and parallel-to-serial conversion on outgoing data. The
differential interface data serializers and deserializers (SERDES) are automatically
constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS
megafunction.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation