EP4CE30F29C7N Datasheet, PDF (131/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
6–25
Table 6–6 and Table 6–7 summarize which I/O banks support these I/O standards in
the Cyclone IV device family.
Table 6–6. Differential I/O Standards Supported in Cyclone IV E I/O Banks
Differential I/O Standards
I/O Bank Location
External Resistor
Network at Transmitter
Transmitter (TX)
Receiver (RX)
LVDS
1,2,5,6
Not Required
v
v
All
Three Resistors
1,2,5,6
Not Required
RSDS
3,4,7,8
Three Resistors
v
—
All
Single Resistor
mini-LVDS
1,2,5,6
Not Required
v
—
All
Three Resistors
PPDS
1,2,5,6
Not Required
v
—
All
Three Resistors
BLVDS ⁽¹⁾
All
Single Resistor
v
v
LVPECL ⁽²⁾
All
—
—
v
Differential SSTL-2 ⁽³⁾
All
Differential SSTL-18 ⁽³⁾
All
—
v
v
—
v
v
Differential HSTL-18 ⁽³⁾
All
Differential HSTL-15 ⁽³⁾
All
—
v
v
—
v
v
Differential HSTL-12 ⁽³⁾, ⁽⁴⁾
All
—
v
v
Notes to Table 6–6:
(1) Transmitter and Receiver f_MAX depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(4) Differential HSTL-12 Class II is supported only in column I/O banks.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1