EP4CE30F29C7N Datasheet, PDF (340/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–60
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–55 shows the transceiver channel datapath and clocking when configured in
GIGE mode.
Figure 1–55. Transceiver Channel Datapath and Clocking when Configured in GIGE Mode
FPGA
Fabric
tx_datain
tx_clkout
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
Transmitter Channel PMA
Serializer
high-speed
clock
low-speed clock
Receiver Channel PCS
Receiver Channel PMA
rx_dataout
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
Deserial-
izer
CDR
(2)
CDR clock
rx_recovclkout ⁽³⁾
Notes to Figure 1–55:
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
(3) Optional rx_recovclkout port from CDR low-speed recovered clock is available for applications such as Synchronous Ethernet.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation