EP4CE30F29C7N Datasheet, PDF (111/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 6: I/O Features in Cyclone IV Devices
6–5
I/O Element Features
f For the specific sustaining current for each V_CCIO voltage level driven through the
resistor and for the overdrive current used to identify the next driven input level, refer
to the Cyclone IV Device Datasheet chapter.
Programmable Pull-Up Resistor
Each Cyclone IV device I/O pin provides an optional programmable pull-up resistor
while in user mode. If you enable this feature for an I/O pin, the pull-up resistor
holds the output to the V_CCIO level of the output pin’s bank.
1 If you enable the programmable pull-up resistor, the device cannot use the bus-hold
feature. Programmable pull-up resistors are not supported on the dedicated
configuration, JTAG, and dedicated clock pins.
1 When the optional DEV_OE signal drives low, all I/O pins remains tri-stated even with
the programmable pull-up option enabled.
Programmable Delay
The Cyclone IV IOE includes programmable delays to ensure zero hold times,
minimize setup times, increase clock-to-output times, and delay the clock input
signal.
A path in which a pin directly drives a register may require a programmable delay to
ensure zero hold time, whereas a path in which a pin drives a register through
combinational logic may not require the delay. Programmable delays minimize setup
time. The Quartus II Compiler can program these delays to automatically minimize
setup time while providing a zero hold time. Programmable delays can increase the
register-to-pin delays for output registers. Each dual-purpose clock input pin
provides a programmable delay to the global clock networks.
Table 6–1 shows the programmable delays for Cyclone IV devices.
Table 6–1. Cyclone IV Devices Programmable Delay Chain
Programmable Delay
Quartus II Logic Option
Input pin-to-logic array delay
Input pin-to-input register delay
Output pin delay
Dual-purpose clock input pin
delay
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Input delay from dual-purpose clock pin to fan-out destinations
There are two paths in the IOE for an input to reach the logic array. Each of the two
paths can have a different delay. This allows you to adjust delays from the pin to the
internal logic element (LE) registers that reside in two different areas of the device.
You must set the two combinational input delays with the input delay from pin to
internal cells logic option in the Quartus II software for each path. If the pin uses the
input register, one of the delays is disregarded and the delay is set with the input
delay from pin to input register logic option in the Quartus II software.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1