EP4CE30F29C7N Datasheet, PDF (100/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

5–38
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Figure 5–25 shows the scan chain bit order sequence for one PLL post-scale counter in
PLLs of Cyclone IV devices.
Figure 5–25. Scan Chain Bit Order
HB
HB
HB
HB
HB
HB
HB
HB
HB
HB
0
1
2
3
4
5
6
7
8
9
rbypass
DATAIN
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
DATAOUT
0
1
2
3
4
5
6
7
8
9
rselodd
Charge Pump and Loop Filter
You can reconfigure the charge pump and loop filter settings to update the PLL
bandwidth in real time. Table 5–8 through Table 5–10 list the possible settings for
charge pump current (I_CP), loop filter resistor (R), and capacitor (C) values for PLLs of
Cyclone IV devices.
Table 5–8. Charge Pump Bit Control
CP[2]
CP[1]
0
0
1
0
1
1
1
1
CP[0]
0
0
0
1
Setting (Decimal)
0
1
3
7
Table 5–9. Loop Filter Resistor Value Control
LFR[4]
LFR[3]
LFR[2]
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
LFR[1]
0
1
0
0
0
1
0
0
1
0
1
LFR[0]
0
1
0
0
0
1
0
0
1
0
0
Setting
(Decimal)
0
3
4
8
16
19
20
24
27
28
30
Cyclone IV Device Handbook,
Volume 1
October 2012 Altera Corporation