EP4CE30F29C7N Datasheet, PDF (430/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

3–32
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Option 2: Use the Respective Channel Transmitter Core Clocks
■ Enable this option if you want the individual transmitter channel’s tx_clkout
signal to provide the read clock to its respective Receive Phase Compensation
FIFO.
■ This option is typically enabled when all the transceiver channels have rate
matching enabled with different data rates and are reconfigured to another Basic
or Protocol functional mode with rate matching enabled.
Figure 3–14 shows the respective tx_clkout of each channel clocking the respective
channels of a transceiver block.
Figure 3–14. Option 2 for Receiver Core Clocking (Channel Reconfiguration Mode)
FPGA Fabric
Transceiver Block
tx_clkout[0]
TX0
RX0
tx_clkout[1]
tx_clkout[2]
TX1
RX1
TX2 (1)
RX2 (1)
TX3 (1)
RX3 (1)
MPLL
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Note to Figure 3–14:
(1) Assuming channel 2 and 3 are running at the same data rate with rate matcher enabled and are reconfigured to another Basic or Protocol functional
mode with rate matching enabled.
Cyclone IV Device Handbook,
Volume 2
November 2011 Altera Corporation