EP4CE30F29C7N Datasheet, PDF (294/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–14
Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
■ Programmable equalization—boosts the high-frequency gain of the incoming
signal up to 7 dB. This compensates for the low-pass filter effects of the
transmission media. The amount of high-frequency gain required depends on the
loss characteristics of the physical medium.
■ Programmable DC gain—provides equal boost to incoming signal across the
frequency spectrum with DC gain settings up to 6 dB.
■ Programmable differential OCT—provides calibrated OCT at 100  or 150 with
on-chip receiver common mode voltage at 0.82 V. The common mode voltage is tri-
stated when you disable the OCT to use external termination.
■ Offset cancellation—corrects the analog offset voltages that might exist from
process variations between the positive and negative differential signals in the
equalizer stage and CDR circuit.
■ Signal detection—detects if the signal level present at the receiver input buffer is
higher than the threshold with a built-in signal threshold detection circuitry. The
circuitry has a hysteresis response that filters out any high-frequency ringing
caused by ISI effects or high-frequency losses in the transmission medium.
Detection is indicated by the assertion of the rx_signaldetect signal. Signal
detection is only supported when 8B/10B encoder/decoder block is enabled.
When not supported, the rx_signaldetect signal is forced high, bypassing the
signal detection function.
1 Disable OCT to use external termination if the link requires a 85  termination, such
as when you are interfacing with certain PCIe Gen1 or Gen2 capable devices.
f For specifications on programmable equalization and DC gain settings, refer to the
Cyclone IV Device Data Sheet.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation