EP4CE30F29C7N Datasheet, PDF (300/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–20
Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Table 1–4 lists the synchronization state machine parameters for the word aligner in
this mode.
Table 1–4. Synchronization State Machine Parameters
Parameter
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the
error count by one
Allowed Values
1–64
1–256
After deassertion of the rx_digitalreset signal in automatic synchronization state
machine mode, the word aligner starts looking for the synchronization code groups,
word alignment pattern or its complement in the received data stream. When the
programmed number of valid synchronization code groups or ordered sets are
received, the rx_syncstatus signal is driven high to indicate that synchronization is
acquired. The rx_syncstatus signal is constantly driven high until the programmed
number of erroneous code groups are received without receiving intermediate good
groups; after which the rx_syncstatus signal is driven low. The word aligner
indicates loss of synchronization (rx_syncstatus signal remains low) until the
programmed number of valid synchronization code groups are received again.
In addition to restoring word boundaries, the word aligner supports the following
features:
■ Programmable run length violation detection—detects consecutive 1s or 0s in the
data stream, and asserts run length violation signal (rx_rlv) when a preset run
length threshold (maximum number of consecutive 1s or 0s) is detected. The
rx_rlv signal in each channel is clocked by its parallel recovered clock and is
asserted for a minimum of two recovered clock cycles to ensure that the FPGA
fabric clock can latch the rx_rlv signal reliably because the FPGA fabric clock
might have phase differences, ppm differences (in asynchronous systems), or both,
with the recovered clock. Table 1–5 lists the run length violation circuit detection
capabilities.
Table 1–5. Run Length Violation Circuit Detection Capabilities
Supported Data Width
Detector Range
Minimum
Maximum
8-bit
4
128
10-bit
5
160
Increment Step
Settings
4
5
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation