EP4CE30F29C7N Datasheet, PDF (346/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–66
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–61 shows the transceiver configuration in Serial RapidIO mode.
Figure 1–61. Transceiver Configuration in Serial RapidIO Mode
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
SRIO
×1
Disabled
Automatic Synchronization
State Machine (10-Bit)
Enabled
Enabled
Disabled
Enabled
Enabled
1.25/2.5/
3.125
Disabled
16-Bit
62.5/125/
156.25
1.25/2.5/
3.125
Disabled
16-Bit
62.5/125/
156.25
Lane Synchronization
In Serial RapidIO mode, the word aligner is compliant to the SRIO Specification 1.3
and is configured in automatic synchronization state machine mode with the
parameter settings as listed in Table 1–20.
Table 1–20. Synchronization State Machine Parameters ⁽¹⁾
Parameter
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to Table 1–20:
(1) The word aligner supports 10-bit pattern lengths in SRIO mode.
Value
127
3
255
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation