EP4CE30F29C7N Datasheet, PDF (423/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
3–25
Table 3–5. rx_dataoutfull[31..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 2 of 3)
FPGA Fabric-Transceiver Channel Receive Signal Description (Based on Cyclone IV GX Supported FPGA
Interface Description
Fabric-Transceiver Channel Interface Widths)
Two 8-bit unencoded Data (rx_dataout)
rx_dataoutfull[7:0] - rx_dataout (LSByte) and
rx_dataoutfull[23:16]- rx_dataout (MSByte)
16-bit FPGA fabric-Transceiver
Channel Interface with PCS-PMA
set to 8/10 bits
The following signals are used in 16-bit 8B/10B modes:
Two Control Bits
rx_dataoutfull[8] - rx_ctrldetect (LSB) and
rx_dataoutfull[24]- rx_ctrldetect (MSB)
Two Receiver Error Detect Bits
rx_dataoutfull[9] - rx_errdetect (LSB) and
rx_dataoutfull[25]- rx_errdetect (MSB)
Two Receiver Sync Status Bits
rx_dataoutfull [10] - rx_syncstatus (LSB) and
rx_dataoutfull[26] - rx_syncstatus (MSB)
Two Receiver Disparity Error Bits
rx_dataoutfull [11] - rx_disperr (LSB) and
rx_dataoutfull[27] - rx_disperr (MSB)
Two Receiver Pattern Detect Bits
rx_dataoutfull[12] - rx_patterndetect (LSB) and
rx_dataoutfull[28]- rx_patterndetect (MSB)
rx_dataoutfull[13] and rx_dataoutfull[29]: Rate Match FIFO deletion status
indicator (rx_rmfifodatadeleted) in non-PCI Express (PIPE) functional modes
rx_dataoutfull[14] and rx_dataoutfull[30]: Rate Match FIFO insertion status
indicator (rx_rmfifodatainserted) in non-PCI Express (PIPE) functional modes
Two 2-bit PCI Express (PIPE) Functional Mode Status Bits
rx_dataoutfull[14:13] - rx_pipestatus (LSB) and rx_dataoutfull[30:29] -
rx_pipestatus (MSB)
rx_dataoutfull[15] and rx_dataoutfull[31]: 8B/10B running disparity
indicator (rx_runningdisp)
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 2