EP4CE30F29C7N Datasheet, PDF (323/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
1–43
In configuration with rate match FIFO, the transmitter datapath clocking is identical
to Transmitter Only operation as shown in Figure 1–38. In each bonded receiver
channel, the CDR unit recovers the clock from serial received data and generates the
high- and low-speed recovered clock for each bonded channel. The high-speed
recovered clock feeds the channel's deserializer, and low-speed recovered clock is
forwarded to receiver PCS. The individual low-speed recovered clock feeds to the
following blocks in the receiver PCS:
■ word aligner
■ write clock of rate match FIFO
The common bonded low-speed clock that is used in all bonded transmitter PCS
datapaths feeds the following blocks in each bonded receiver PCS:
■ read clock of rate match FIFO
■ 8B/10B decoder
■ write clock of byte deserializer
■ byte ordering
■ write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the common bonded low-speed clock
frequency is halved before feeding to the write clock of RX phase compensation FIFO.
The common bonded low-speed clock is available in FPGA fabric as coreclkout port,
which can be used in FPGA fabric to send transmitter data and control signals, and
capture receiver data and status signals from the bonded channels.
FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface clocks consists of clock signals from the FPGA
fabric to the transceiver blocks, and from the transceiver blocks to the FPGA fabric.
These clock resources use the global clock networks (GCLK) in the FPGA core.
f For information about the GCLK resources in the Cyclone IV GX devices, refer to
Clock Networks and PLLs in Cyclone IV Devices chapter.
Table 1–11 lists the FPGA fabric-transceiver interface clocks.
Table 1–11. FPGA Fabric-Transceiver Interface Clocks (Part 1 of 2)
Clock Name
tx_clkout
rx_clkout
coreclkout
fixed_clk
reconfig_clk ⁽¹⁾, ⁽²⁾
Clock Description
Phase compensation FIFO clock
Phase compensation FIFO clock
Phase compensation FIFO clock
125MHz receiver detect clock in PIPE
mode
Transceiver dynamic reconfiguration and
offset cancellation clock
Interface Direction
Transceiver to FPGA fabric
Transceiver to FPGA fabric
Transceiver to FPGA fabric
FPGA fabric to transceiver
FPGA fabric to transceiver
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2