EP4CE30F29C7N Datasheet, PDF (126/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Each Cyclone IV I/O bank has a VREF bus to accommodate voltage-referenced I/O standards. Each VREF pin is the reference
source for its V_REF group. If you use a V_REF group for voltage-referenced I/O standards, connect the VREF pin for that group to
the appropriate voltage level. If you do not use all the V_REF groups in the I/O bank for voltage-referenced I/O standards, you
can use the VREF pin in the unused voltage-referenced groups as regular I/O pins. For example, if you have SSTL-2 Class I
input pins in I/O bank 1 and they are all placed in the VREFB1N[0] group, VREFB1N[0] must be powered with 1.25 V, and the
remaining VREFB1N[1..3] pins (if available) are used as I/O pins. If multiple V_REF groups are used in the same I/O bank, the
VREF pins must all be powered by the same voltage level because the VREF pins are shorted together within the same I/O bank.
1 When VREF pins are used as regular I/Os, they have higher pin capacitance than regular user I/O pins. This has an impact on
the timing if the pins are used as inputs and outputs.
f For more information about VREF pin capacitance, refer to the pin capacitance section in the Cyclone IV Device Datasheet chapter.
f For information about how to identify V_REF groups, refer to the Cyclone IV Device Pin-Out files or the Quartus II Pin Planner
tool.
Table 6–4 and Table 6–5 summarize the number of VREF pins in each I/O bank for the Cyclone IV device family.
Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices (Part 1 of 2)
I/O
Bank
(1)
1 111111222222111444444422233333
2 111111222222111444444422233333
3 111111222222111444444422233333
4 111111222222111444444422233333
5 111111222222111444444422233333
6 111111222222111444444422233333
7 111111222222111444444422233333