EP4CE30F29C7N Datasheet, PDF (338/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–58
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
The compliance pattern is a repeating sequence of the four code groups: /K28.5/;
/D21.5/; /K28.5/; /D10.2/. Figure 1–53 shows the compliance pattern transmission
where the tx_forcedispcompliance port must be asserted in the same parallel clock
cycle as /K28.5/D21.5/ of the compliance pattern on tx_datain[15..0] port.
Figure 1–53. Compliance Pattern Transmission Support in PCI Express (PIPE) Mode
/K28.5/D21.5/ /K28.5/D10.2/ /K28.5/D21.5/ /K28.5/D10.2/
tx_datain[15..0]
B5BC
4ABC
B5BC
4ABC
tx_ctrldetect[1..0]
01
tx_forcedispcompliance
Reset Requirement
Cyclone IV GX devices meets the PCIe reset time requirement from device power up
to the link active state with the configuration schemes listed in Table 1–17.
Table 1–18. Electrical Idle Inference Conditions
Device
EP4CGX15
EP4CGX22
EP4CGX30 ⁽¹⁾
EP4CGX50
EP4CGX75
EP4CGX110
EP4CGX150
Configuration Scheme
Passive serial (PS)
PS
PS
Fast passive parallel (FPP)
FPP
FPP
FPP
Configuration Time (ms)
51
92
92
41
41
70
70
Note to Table 1–18:
(1) EP4CGX30 device in F484 package fulfills the PCIe reset time requirement using FPP configuration scheme with
configuration time of 41 ms.
GIGE Mode
GIGE mode provides the transceiver channel datapath configuration for GbE
(specifically the 1000 Base-X physical layer device (PHY) standard) protocol
implementation. The Cyclone IV GX transceiver provides the PMA and the following
PCS functions as defined in the IEEE 802.3 specification for 1000 Base-X PHY:
■ 8B/10B encoding and decoding
■ synchronization
■ upstream transmitter and local receiver clock frequency compensation (rate
matching)
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation