EP4CE30F29C7N Datasheet, PDF (293/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
1–13
In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at
the receiver input buffer as shown in Figure 1–13. The link common mode voltage
depends on the transmitter common mode voltage and the receiver common mode
voltage. When using the receiver OCT and on-chip biasing circuitry in a DC coupled
link, you must ensure the transmitter common mode voltage is compatible with the
receiver common mode requirements. If you disable the OCT, you must terminate and
bias the receiver externally and ensure compatibility between the transmitter and the
receiver common mode voltage.
Figure 1–13. DC-Coupled Link with OCT
Transmitter
Receiver
Physical Medium
TX Termination
Physical Medium
RX Termination
TX
RX
V_CM
V_CM
Figure 1–14 shows the receiver input buffer block diagram.
Figure 1–14. Receiver Input Buffer Block Diagram
Receiver Input Buffer
rx_datain
Equalization
and
DC Gain
Circuitry
50 or 75 
50  or 75 
RX
V_CM
Signal
Threshold
Detection
Circuitry
To CDR
Signal
Detect
The receiver input buffers support the following features:
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2