EP4CE30F29C7N Datasheet, PDF (314/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–34
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484
and Larger Packages
(1)
MPLL_8
(2)
GPLL_2
(3)
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL1 ^Ch1
TX PMA
Ch0
MPLL_7
(3)
MPLL_6
(3)
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
Not applicable in
F484 package
MPLL_5
(2)
(1) _{GPLL_1}
(3)
Notes to Figure 1–32:
(1) High-speed clock.
(2) Low-speed clock.
(3) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
Table 1–9.
The transceiver datapath clocking varies in non-bonded channel configuration
depending on the PCS configuration.
Figure 1–33 shows the datapath clocking in transmitter only operation. In this mode,
each channel selects the high- and low-speed clock from one of the supported PLLs.
The high-speed clock feeds to the serializer for parallel to serial operation. The
low-speed clock feeds to the following blocks in the transmitter PCS:
■ 8B/10B encoder
■ read clock of the byte serializer
■ read clock of the TX phase compensation FIFO
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation