EP4CE30F29C7N Datasheet, PDF (391/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
2–17
PCIe Functional Mode
You can configure PCIe functional mode with or without the receiver clock rate
compensation FIFO in the Cyclone IV GX device. The reset sequence remains the
same whether or not you use the receiver clock rate compensation FIFO.
PCIe Reset Sequence
The PCIe protocol consists of an initialization/compliance phase and a normal
operation phase. The reset sequences for these two phases are described based on the
timing diagram in Figure 2–10.
Figure 2–10. Reset Sequence of PCIe Functional Mode ⁽¹⁾, ⁽²⁾
Initialization / Compliance Phase
Normal Operation Phase
Reset / Power Down Signals
1
pll_areset
tx_digitalreset
rx_analogreset
rx_digitalreset
Output Status Signals
pll_locked
busy (5)
rx_freqlocked
1 μs
2
4
6
7
Two parallel
clock cycles
3
5
8
11 12
>_ two parallel
clock cycles
9
10
t_{LTD_Manual} (3)
t_{LTD_Auto} (4)
Ignore receive data
Notes to Figure 2–10:
(1) This timing diagram is drawn based on the PCIe Gen 1 ×1 mode.
(2) For bonded PCIe Gen 1 ×2 and ×4 modes, there will be additional rx_freqlocked[n] signal. n=number of channels.
(3) For t_{LTD_Manual} duration, refer to the Cyclone IV Device Datasheet chapter.
(4) For t_{LTD_Auto} duration, refer to the Cyclone IV Device Datasheet chapter.
(5) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the busy
signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2