EP4CE30F29C7N Datasheet, PDF (318/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–38
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–36 and Figure 1–37 show the independent high-speed clock and bonded
low-speed clock distributions for transceivers in F324 and smaller packages, and in
F484 and larger packages in bonded (×2 and ×4) channel configuration.
Figure 1–36. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in
F324 and Smaller Packages.
+ _{2 Bonded Channel Configuration}
+ _{4 Bonded Channel Configuration}
(2)
MPLL_2
(3)
Ch3 TX PMA
(1)
Ch2 TX PMA
Transceiver (1)
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
(4)
(2)
MPLL_2
(3)
Ch3 TX PMA
(1)
Ch2 TX PMA
Transceiver (1)
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
(4)
MPLL_1
MPLL_1
Notes to Figure 1–36:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
(4) Bonded common low-speed clock path.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation