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EP4CE30F29C7N Datasheet, PDF (291/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1 | |||
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Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
1â11
Receiver Channel Datapath
The following sections describe the Cyclone IV GX receiver channel datapath
architecture as shown in Figure 1â3 on page 1â4:
â âReceiver Input Bufferâ on page 1â11
â âClock Data Recoveryâ on page 1â15
â âDeserializerâ on page 1â16
â âWord Alignerâ on page 1â17
â âDeskew FIFOâ on page 1â22
â âRate Match FIFOâ on page 1â23
â â8B/10B Decoderâ on page 1â23
â âByte Deserializerâ on page 1â24
â âByte Orderingâ on page 1â24
â âRX Phase Compensation FIFOâ on page 1â25
Receiver Input Buffer
Table 1â2 lists the electrical features supported by the Cyclone IV GX receiver input
buffer.
Table 1â2. Electrical Features Supported by the Receiver Input Buffer
I/O Standard
Programmable Common
Mode Voltage (V)
Coupling
1.4-V PCML
0.82
AC, DC
1.5-V PCML
0.82
AC, DC
2.5-V PCML
0.82
AC
LVPECL
LVDS
0.82
AC
0.82
AC, DC (1)
Note to Table 1â2:
(1) DC coupling is supported for LVDS with lower on-chip common mode voltage of 0.82 V.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2
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