EP4CE30F29C7N Datasheet, PDF (328/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–48
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 2 of 2)
Functional Mode
Protocol
Key Feature
Deterministic
Latency
Proprietary, CPRI, TX PLL phase frequency detector (PFD) feedback,
OBSAI
registered mode FIFO, TX bit-slip control
SDI
SDI
High-speed SERDES, CDR
Reference
“Deterministic Latency
Mode” on page 1–73
“SDI Mode” on
page 1–76
Basic Mode
The Cyclone IV GX transceiver channel datapath is highly flexible in Basic mode to
implement proprietary protocols. SATA, V-by-One, and Display Port protocol
implementations in Cyclone IV GX transceiver are supported with Basic mode.
Figure 1–44 shows the transceiver channel datapath supported in Basic mode.
Figure 1–44. Transceiver Channel Datapath in Basic Mode
FPGA
Fabric
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
Transmitter Channel PMA
Serializer
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
Receiver Channel PCS
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Receiver Channel PMA
Word
Aligner
Deserial-
izer
CDR
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation