EP4CE30F29C7N Datasheet, PDF (127/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices (Part 2 of 2)
I/O
Bank
(1)
8 111111222222111444444422233333
Note to Table 6–4:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
Table 6–5. Number of VREF Pins Per I/O Bank for Cyclone IV GX Devices
Device
4CGX15
4CGX22
4CGX30
4CGX50
4CGX75
4CGX110
4CGX150
I/O Bank
(1)
3
1
1
1
3
3
3
3
3
4
1
1
1
3
3
3
3
3
5
1
1
1
3
3
3
3
3
6
1
1
1
3
3
3
3
3
7
1
1
1
3
3
3
3
3
8 ⁽²⁾
1
1
1
3
3
3
3
3
Notes to Table 6–5:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) Bank 9 does not have VREF pin. If input pins with VREF I/O standards are used in bank 9 during user mode, it shares the VREF pin in bank 8.
Each Cyclone IV I/O bank has its own VCCIO pins. Each I/O bank can support only one V_CCIO setting from among 1.2, 1.5, 1.8,
2.5, 3.0, or 3.3 V. Any number of supported single-ended or differential standards can be simultaneously supported in a single
I/O bank, as long as they use the same V_CCIO levels for input and output pins.