EP4CE30F29C7N Datasheet, PDF (435/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Cyclone IV Dynamic Reconfiguration
Functional Simulation of the Dynamic Reconfiguration Process
3–37
Functional Simulation of the Dynamic Reconfiguration Process
This section describes the points to be considered during functional simulation of the
dynamic reconfiguration process.
■ You must connect the ALTGX_RECONFIG instance to the
ALTGX_instance/ALTGX instances in your design for functional simulation.
■ The functional simulation uses a reduced timing model of the dynamic
reconfiguration controller. The duration of the offset cancellation process is 16
reconfig_clk clock cycles for functional simulation only.
■ The gxb_powerdown signal must not be asserted during the offset cancellation
sequence (for functional simulation and silicon).
Document Revision History
Table 3–8 lists the revision history for this chapter.
Table 3–8. Document Revision History
Date
November 2011
December 2010
July 2010
Version
2.1
2.0
1.0
Changes
■ Updated “Dynamic Reconfiguration Controller Architecture”, “PMA Controls
Reconfiguration Mode”, “PLL Reconfiguration Mode”, and “Error Indication During
Dynamic Reconfiguration” sections.
■ Updated Table 3–2 and Table 3–4.
■ Updated for the Quartus II software version 10.1 release.
■ Updated Table 3–1, Table 3–2, Table 3–3, Table 3–4, Table 3–5, and Table 3–6.
■ Added Table 3–7.
■ Updated Figure 3–1, Figure 3–11, Figure 3–13, and Figure 3–14.
■ Updated “Offset Cancellation Feature”, “Error Indication During Dynamic
Reconfiguration”, “Data Rate Reconfiguration Mode Using RX Local Divider”, “PMA
Controls Reconfiguration Mode”, and “Control and Status Signals for Channel
Reconfiguration” sections.
Initial release.
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 2