EP4CE30F29C7N Datasheet, PDF (408/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

3–10
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 7 of 7)
Port Name
Input/
Output
Description
This signal is always available for you to select in the Channel reconfiguration screen. This
signal is applicable only in the dynamic reconfiguration modes grouped under Channel
reconfiguration mode including channel interface and Use RX local divider option.
reconfig_address
_out[5..0]
Output
This signal represents the current address used by the ALTGX_RECONFIG instance when
writing the .mif into the transceiver channel. This signal increments by 1, from 0 to the last
address, then starts at 0 again. You can use this signal to indicate the end of all the .mif
write transactions (reconfig_address_out[5..0] changes from the last address to 0 at
the end of all the .mif write transactions).
reconfig_address
_en
Output
This is an optional signal you can select in the Channel reconfiguration screen. This signal
is applicable only in dynamic reconfiguration modes grouped under the Channel
reconfiguration option.
The dynamic reconfiguration controller asserts reconfig_address_en to indicate that
reconfig_address_out[5..0] has changed. This signal is asserted only after the
dynamic reconfiguration controller completes writing one 16-bit word of the .mif.
reset_reconfig_
address
Input
This is an optional signal you can select in the Channel reconfiguration screen. This signal
is applicable only in dynamic reconfiguration modes grouped under the Channel
reconfiguration option.
Enable this signal and assert it for one reconfig_clk clock cycle if you want to reset the
reconfiguration address used by the ALTGX_RECONFIG instance during reconfiguration.
reconfig_data
[15..0]
Input
This signal is applicable only in the dynamic reconfiguration modes grouped under the
Channel reconfiguration option. This is a 16-bit word carrying the reconfiguration
information. It is stored in a .mif that you must generate. The ALTGX_RECONFIG instance
requires that you provide reconfig_data [15..0]on every .mif write transaction using
the write_all signal.
reconfig_reset ⁽⁴⁾
Input
You can use this signal to reset all the reconfiguration process in Channel reconfiguration
mode. Asserting this port will reset all the register in the reconfiguration controller logics.
This port only shows up in Channel reconfiguration mode.
If you are feeding into this port, synchronize the reset signal to the reconfig_clk
domain.
channel_reconfig
_done
Output
This signal goes high to indicate that the dynamic reconfiguration controller has finished
writing all the words of the .mif. The channel_reconfig_done signal is automatically
deasserted at the start of a new dynamic reconfiguration write sequence. This signal is
applicable only in channel reconfiguration mode.
Notes to Table 3–2:
(1) Not all combinations of input bits are legal values.
(2) This setting is required for compliance to PCI Express^® (PIPE) functional mode.
(3) PLL reconfiguration is performed using ALTPLL_RECONFIG controller. Hence it is not selected through the reconfig_mode_sel[2..0] port.
(4) reconfig_reset will not restart the offset cancellation operation. Offset cancellation only occurs one time after power up and does not occur
when subsequent reconfig_reset is asserted.
Offset Cancellation Feature
The Cyclone IV GX devices provide an offset cancellation circuit per receiver channel
to counter the offset variations due to process, voltage, and temperature (PVT). These
variations create an offset in the analog circuit voltages, pushing them out of the
expected range. In addition to reconfiguring the transceiver channel, the dynamic
reconfiguration controller performs offset cancellation on all receiver channels
connected to it on power up.
Cyclone IV Device Handbook,
Volume 2
November 2011 Altera Corporation