EP4CE30F29C7N Datasheet, PDF (187/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
8–23
f For more information about the operation of the Micron P30 Parallel NOR and P33
Parallel NOR flash memories, search for the keyword “P30” or “P33” on the Micron
website (www.micron.com) to obtain the P30 or P33 family datasheet.
Single-Device AP Configuration
The following groups of interface pins are supported in Micron P30 and P33 flash
memories:
■ Control pins
■ Address pins
■ Data pins
The following control signals are from the supported parallel flash memories:
■ CLK
■ active-low reset (RST#)
■ active-low chip enable (CE#)
■ active-low output enable (OE#)
■ active-low address valid (ADV#)
■ active-low write enable (WE#)
The supported parallel flash memories output a control signal (WAIT) to Cyclone IV E
devices to indicate when synchronous data is ready on the data bus. Cyclone IV E
devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the flash
memory. A 16-bit bidirectional data bus (DATA[15..0]) provides data transfer between
the Cyclone IV E device and the flash memory.
The following control signals are from the Cyclone IV E device to flash memory:
■ DCLK
■ active-low hard rest (nRESET)
■ active-low chip enable (FLASH_nCE)
■ active-low output enable for the DATA[15..0] bus and WAIT pin (nOE)
■ active-low address valid signal and is used to write data into the flash (nAVD)
■ active-low write enable and is used to write data into the flash (nWE)
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1