EP4CE30F29C7N Datasheet, PDF (208/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–44
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
f For more information about configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in volume 2 of the
Configuration Handbook.
FPP Configuration Timing
Figure 8–22 shows the timing waveform for the FPP configuration when using an
external host.
Figure 8–22. FPP Configuration Timing Waveform ⁽¹⁾
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[7..0]
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Byte 0 Byte 1
t_DSU
Byte 2
Byte 3
User I/O User mode Tri-stated with internal pull-up resistor
INIT_DONE
Byte n-1 Byte n
(4)
(5)
User Mode
User Mode
t_CD2UM
Notes to Figure 8–22:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone IV device holds nSTATUS low during POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0] is available as a user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
settings.
Table 8–13 lists the FPP configuration timing parameters for Cyclone IV devices.
Table 8–13. FPP Timing Parameters for Cyclone IV Devices (Part 1 of 2)
Symbol
Parameter
t_CF2CD
nCONFIG low to
CONF_DONE low
Minimum
Cyclone IV ⁽¹⁾ Cyclone IV E ⁽²⁾
—
Maximum
Unit
Cyclone IV ⁽¹⁾ Cyclone IV E ⁽²⁾
500
ns
nCONFIG low to
t_CF2ST0
nSTATUS low
—
500
ns
nCONFIG low pulse
t_CFG
width
500
—
ns
nSTATUS low pulse
t_STATUS
width
45
230 ⁽³⁾
µs
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation