EP4CE30F29C7N Datasheet, PDF (117/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 6: I/O Features in Cyclone IV Devices
I/O Standards
6–11
Figure 6–4 shows the single-ended I/O standards for OCT without calibration. The R_S
shown is the intrinsic transistor impedance.
Figure 6–4. Cyclone IV Devices R_S OCT Without Calibration
Cyclone IV Device
Driver Series Termination
V_CCIO
Receiving
Device
R_S
Z_O
R_S
GND
All I/O banks and I/O pins support impedance matching and series termination.
Dedicated configuration pins and JTAG pins do not support impedance matching or
series termination.
R_S OCT is supported on any I/O bank. V_CCIO and V_REF must be compatible for all I/O
pins to enable R_S OCT in a given I/O bank. I/O standards that support different R_S
values can reside in the same I/O bank as long as their V_CCIO and V_REF do not conflict.
Impedance matching is implemented using the capabilities of the output driver and is
subject to a certain degree of variation, depending on the process, voltage, and
temperature.
f For more information about tolerance specification, refer to the Cyclone IV Device
Datasheet chapter.
I/O Standards
Cyclone IV devices support multiple single-ended and differential I/O standards.
Cyclone IV devices support 3.3-, 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-V I/O standards.
Table 6–3 summarizes I/O standards supported by Cyclone IV devices and which
I/O pins support them.
Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 1 of 3)
I/O Standard
3.3-V LVTTL,
3.3-V LVCMOS ⁽²⁾
3.0-V LVTTL,
3.0-V LVCMOS ⁽²⁾
Type
Standard
Support
Single-ended JESD8-B
Single-ended JESD8-B
V_CCIO Level (in V)
Column I/O Pins
Input
Output
CLK,
DQS
PLL_OUT
User
I/O
Pins
3.3/3.0/2.5
(3)
3.3
v
v
v
3.3/3.0/2.5
(3)
3.0
v
v
v
Row I/O Pins ⁽¹⁾
CLK, User I/O
DQS Pins
v
v
v
v
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1