EP4CE30F29C7N Datasheet, PDF (312/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–32
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Table 1–9 lists the high- and low-speed clock sources for each channel.
Table 1–9. High- and Low-Speed Clock Sources for Each Channel in Non-Bonded Channel Configuration
Package
Transceiver Block Transceiver Channel
F324 and smaller
GXBL0
All channels
F484 and larger
GXBL0
GXBL1 ⁽¹⁾
Channels 0, 1
Channels 2, 3
Channels 0, 1
Channels 2, 3
Note to Table 1–9:
(1) MPLL_7 and GXBL1 are not applicable for transceivers in F484 package
High- and Low-Speed Clocks Sources
Option 1
Option 2
MPLL_1
MPLL_5/GPLL_1
MPLL_5
MPLL_7/MPLL_6
MPLL_7
MPLL_2
MPLL_6
MPLL_6/MPLL_7 ⁽¹⁾
MPLL_8
MPLL_8/GPLL_2
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation