EP4CE30F29C7N Datasheet, PDF (306/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–26
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Transceiver Clocking Architecture
The multipurpose PLLs and general-purpose PLLs located on the left side of the
device generate the clocks required for the transceiver operation. The following
sections describe the Cyclone IV GX transceiver clocking architecture:
■ “Input Reference Clocking” on page 1–27
■ “Transceiver Channel Datapath Clocking” on page 1–29
■ “FPGA Fabric-Transceiver Interface Clocking” on page 1–43
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation