EP4CE30F29C7N Datasheet, PDF (428/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

3–30
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Option 2: Use the Respective Channel Transmitter Core Clocks
■ Enable this option if you want the individual transmitter channel tx_clkout
signals to provide the write clock to their respective Transmit Phase Compensation
FIFOs.
■ This option is typically enabled when each transceiver channel is reconfigured to a
different functional mode using channel reconfiguration.
Figure 3–12 shows how each transmitter channel’s tx_clkout signal provides a clock
to the Transmit Phase Compensation FIFOs of the respective transceiver channels.
Figure 3–12. Option 2 for Transmitter Core Clocking (Channel Reconfiguration Mode)
FPGA Fabric
Transciever Block
tx_clkout[0]
TX0
RX0
tx_clkout[1]
TX1
RX1
tx_clkout[2]
TX2
RX2
MPLL
tx_clkout[3]
TX3
RX3
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Receiver core clocking refers to the clock that is used to read the parallel data from the
Receiver Phase Compensation FIFO into the FPGA fabric. You can use one of the
following clocks to read from the Receive Phase Compensation FIFO:
■ rx_coreclk—you can use a clock of the same frequency as rx_clkout from the
FPGA fabric to provide the read clock to the Receive Phase Compensation FIFO. If
you use rx_coreclk, it overrides the rx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
■ rx_clkout—the Quartus II software automatically routes rx_clkout to the FPGA
fabric and back into the Receive Phase Compensation FIFO.
Cyclone IV Device Handbook,
Volume 2
November 2011 Altera Corporation