EP4CE30F29C7N Datasheet, PDF (334/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
PIPE Interface
The PIPE interface provides a standard interface between the PCIe-compliant PHY
and MAC layer as defined by the version 2.00 of the PIPE Architecture specification
for Gen1 (2.5 Gbps) signaling rate. Any core or IP implementing the PHY MAC, data
link, and transaction layers that supports PIPE 2.00 can be connected to the
Cyclone IV GX transceiver configured in PIPE mode. Table 1–15 lists the PIPE-specific
ports available from the Cyclone IV GX transceiver configured in PIPE mode and the
corresponding port names in the PIPE 2.00 specification.
Table 1–15. Transceiver-FPGA Fabric Interface Ports in PIPE Mode
Transceiver Port Name
PIPE 2.00 Port Name
tx_datain[15..0] ⁽¹⁾
TxData[15..0]
tx_ctrlenable[1..0] ⁽¹⁾
TxDataK[1..0]
rx_dataout[15..0] ⁽¹⁾
RxData[15..0]
rx_ctrldetect[1..0] ⁽¹⁾
RxDataK[1..0]
tx_detectrxloop
TxDetectRx/Loopback
tx_forceelecidle
TxElecIdle
tx_forcedispcompliance
TxCompliance
pipe8b10binvpolarity
RxPolarity
powerdn[1..0] ⁽²⁾
PowerDown[1..0]
pipedatavalid
RxValid
pipephydonestatus
PhyStatus
pipeelecidle
RxElecIdle
pipestatus
RxStatus[2..0]
Notes to Table 1–15:
(1) When used with PCIe hard IP block, the byte SERDES is not used. In this case, the data ports are 8 bits wide and
control identifier is 1 bit wide.
(2) Cyclone IV GX transceivers do not implement power saving measures in lower power states (P0s, P1, and P2),
except when putting the transmitter buffer in electrical idle in the lower power states.
Receiver Detection Circuitry
In PIPE mode, the transmitter supports receiver detection function with a built-in
circuitry in the transmitter PMA. The PCIe protocol requires the transmitter to detect
if a receiver is present at the far end of each lane as part of the link training and
synchronization state machine sequence. This feature requires the following
conditions:
■ transmitter output buffer to be tri-stated
■ have OCT utilization
■ 125 MHz clock on the fixedclk port
The circuit works by sending a pulse on the common mode of the transmitter. If an
active PCIe receiver is present at the far end, the time constant of the step voltage on
the trace is higher compared to when the receiver is not present. The circuitry
monitors the time constant of the step signal seen on the trace to decide if a receiver
was detected.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation