EP4CE30F29C7N Datasheet, PDF (326/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–46
Chapter 1: Cyclone IV Transceivers Architecture
PCI-Express Hard IP Block
The calibration block internally generates a constant internal reference voltage,
independent of PVT variations and uses this voltage and the external reference
resistor on the RREF pin to generate constant reference currents. The OCT calibration
circuit calibrates the OCT resistors present in the transceiver channels. Figure 1–41
shows the calibration block diagram.
Figure 1–41. Input Signals to the Calibration Blocks ⁽¹⁾
RREF pin (2)
cal_blk_clk (3)
cal_blk_powerdown (4)
Calibration Block
Internal
Reference
Voltage
Generator
Reference
Signal
OCT Calibration Control
OCT Calibration
Circuit
Analog Block
Calibration Circuit
Analog Block
Calibration Control
Notes to Figure 1–41:
(1) All transceiver channels use the same calibration block clock and power down signals.
(2) Connect a 2 k (tolerance max ± 1%) external resistor to the RREF pin to ground. The RREF resistor connection in
the board must be free from any external noise.
(3) Supports up to 125 MHz clock frequency. Use either dedicated global clock or divide-down logic from the FPGA fabric
to generate a slow clock on the local clock routing.
(4) The calibration block restarts the calibration process following deassertion of the cal_blk_powerdown signal.
PCI-Express Hard IP Block
Figure 1–42 shows the block diagram of the PCIe hard IP block implementing the
PHY MAC, Data Link Layer, and Transaction Layer for PCIe interfaces. The PIPE
interface is used as the interface between the transceiver and the hard IP block.
Figure 1–42. PCI Express Hard IP High-Level Block Diagram
PCIe Hard IP
Clock & Reset Selection
PCIe Protocol Stack
TL
Interface
Adapter
Retry
Buffer
Virtual
Channel
RX
Buffer
Local
Mnmt IF
(LMI)
PCIe
Reconfig
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation