EP4CE30F29C7N Datasheet, PDF (80/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

5–18
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLLs in Cyclone IV Devices
PLLs in Cyclone IV Devices
Cyclone IV GX devices offer two variations of PLLs: general purpose PLLs and
multipurpose PLLs. Cyclone IV E devices only have the general purpose PLLs.
The general purpose PLLs are used for general-purpose applications in the FPGA
fabric and periphery such as external memory interfaces. The multipurpose PLLs are
used for clocking the transceiver blocks. When the multipurpose PLLs are not used
for transceiver clocking, they can be used for general-purpose clocking.
f For more details about the multipurpose PLLs used for transceiver clocking, refer to
the Cyclone IV Transceivers chapter.
Cyclone IV GX devices contain up to eight general purpose PLLs and multipurpose
PLLs while Cyclone IV E devices have up to four general purpose PLLs that provide
robust clock management and synthesis for device clock management, external
system clock management, and high-speed I/O interfaces.
f For more information about the number of general purpose PLLs and multipurpose
PLLs in each device density, refer to the Cyclone IV Device Family Overview chapter.
1 The general I/O pins cannot drive the PLL clock input pins.
Table 5–5 lists the features available in Cyclone IV GX PLLs.
Table 5–5. Cyclone IV GX PLL Features (Part 1 of 2)
Availability
Features
C (output counters)
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
Spread-spectrum input clock
tracking
PLL cascading
Source-Synchronous Mode
No Compensation Mode
Normal Mode
Zero Delay Buffer Mode
Deterministic Latency
Compensation Mode
Phase shift resolution ⁽⁹⁾
Programmable duty cycle
Output counter cascading
General Purpose PLLs
Multipurpose PLLs
PLL_1
(1), (10)
PLL_2
(1), (10)
PLL_ PLL_ PLL_1 PLL_2 PLL_5 PLL_6 PLL_7 PLL_8
3 ⁽²⁾
4 ⁽³⁾
(4)
(4)
(1), (10) (1), (10)
(1)
(1)
5
1 to 512 ⁽⁵⁾
1 single-ended or 1 differential pair
12 single-ended or 6 differential pairs ⁽⁶⁾
and 4 differential pairs ⁽⁷⁾
v ⁽⁸⁾
Through GCLK
v
v vvvv v
—
—v
v
v vvvv v
v vv
v
v vvvv v
—
—v
v
v vvvv v
—
—v
v
v
——vv v
v vv
Down to 96 ps increments
v
v
Cyclone IV Device Handbook,
Volume 1
October 2012 Altera Corporation