EP4CE30F29C7N Datasheet, PDF (267/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 11: Power Requirements for Cyclone IV Devices
Hot-socketing Feature Implementation
11–3
1 The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are
always enabled (after POR) before and during configuration. The weak pull up
resistors are not enabled prior to POR.
A possible concern for semiconductor devices in general regarding hot socketing is
the potential for latch up. Latch up can occur when electrical subsystems are hot
socketed into an active system. During hot socketing, the signal pins may be
connected and driven by the active system before the power supply can provide
current to the V_CC of the device and ground planes. This condition can lead to latch up
and cause a low-impedance path from V_CC to GND in the device. As a result, the
device extends a large amount of current, possibly causing electrical damage.
The design of the I/O buffers and hot-socketing circuitry ensures that Cyclone IV
devices are immune to latch up during hot-socketing.
f For more information about the hot-socketing specification, refer to the Cyclone IV
Device Datasheet chapter and the Hot-Socketing and Power-Sequencing Feature and Testing
for Altera Devices white paper.
Hot-socketing Feature Implementation
The hot-socketing circuit does not include the CONF_DONE, nCEO, and nSTATUS pins to
ensure that they are able to operate during configuration. The expected behavior for
these pins is to drive out during power-up and power-down sequences.
1 Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To
ensure proper operation, Altera recommends connecting the GND between boards
before connecting the power supplies. This prevents the GND on your board from
being pulled up inadvertently by a path to power through other components on your
board. A pulled up GND can otherwise cause an out-of-specification I/O voltage or
current condition with the Altera device.
Power-On Reset Circuitry
Cyclone IV devices contain POR circuitry to keep the device in a reset state until the
power supply voltage levels have stabilized during power up. During POR, all user
I/O pins are tri-stated until the power supplies reach the recommended operating
levels. In addition, the POR circuitry also ensures the V_CCIO level of I/O banks that
contain configuration pins reach an acceptable level before configuration is triggered.
The POR circuit of the Cyclone IV device monitors the V_CCINT, V_CCA, and V_CCIO that
contain configuration pins during power-on. You can power up or power down the
V_CCINT, V_CCA, and V_CCIO pins in any sequence. The V_CCINT, V_CCA, and V_CCIO must have
a monotonic rise to their steady state levels. All V_CCA pins must be powered to 2.5V
(even when PLLs are not used), and must be powered up and powered down at the
same time.
After the Cyclone IV device enters the user mode, the POR circuit continues to
monitor the V_CCINT and V_CCA pins so that a brown-out condition during user mode is
detected. If the V_CCINT or V_CCA voltage sags below the POR trip point during user
mode, the POR circuit resets the device. If the V_CCIO voltage sags during user mode,
the POR circuit does not reset the device.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1