EP4CE30F29C7N Datasheet, PDF (368/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–88
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 2 of 3)
Block Port Name
rx_rmfifofull
rx_rmfifoempty
rx_ctrldetect
rx_errdetect
RX PCS
rx_disperr
rx_runningdisp
rx_enabyteord
rx_byteorder
alignstatus
rx_dataout
Cyclone IV Device Handbook,
Volume 2
Input/
Output
Clock Domain
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Input Asynchronous signal
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Description
Rate match FIFO full status indicator.
■ A high level indicates the rate match FIFO is full.
■ Driven for a minimum of two serial clock cycles in
configurations without a byte serializer and a
minimum of three recovered clock cycles in
configurations with a byte serializer.
Rate match FIFO empty status indicator.
■ A high level indicates the rate match FIFO is empty.
■ Driven for a minimum of two serial clock cycles in
configurations without a byte serializer and a
minimum of three recovered clock cycles in
configurations with a byte serializer.
8B/10B decoder control or data identifier.
■ A high level indicates received code group is a /Kx.y/
control code group.
■ A low level indicates received code group is a /Dx.y/
data code group.
8B/10B code group violation or disparity error indicator.
■ A high level indicates that a code group violation or
disparity error was detected on the associated
received code group.
■ Use with the rx_disperr signal to differentiate
between a code group violation or a disparity error as
follows: [rx_errdetect:rx_disperr]
■ 2'b00—no error
■ 2'b10—code group violation
■ 2'b11—disparity error or both
8B/10B disparity error indicator.
■ A high level indicates that a disparity error was
detected on the associated received code group.
8B/10B current running disparity indicator.
■ A high level indicates a positive current running
disparity at the end of the decoded byte
■ A low level indicates a negative current running
disparity at the end of the decoded byte
Enable byte ordering control
■ A low-to-high transition triggers the byte ordering
block to restart byte ordering operation.
Byte ordering status indicator.
■ A high level indicates that the byte ordering block has
detected the programmed byte ordering pattern in the
least significant byte of the received data from the
byte deserializer.
Parallel data output from the receiver to the FPGA fabric.
■ Bus width depends on channel width multiplied by
number of channels per instance.
October 2013 Altera Corporation