EP4CE30F29C7N Datasheet, PDF (353/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–73
Clock Rate Compensation
In XAUI mode, the rate match FIFO compensates up to ±100 ppm (200 ppm total)
difference between the upstream transmitter and the local receiver reference clock.
The XAUI protocol requires the transmitter to send /R/ (/K28.0/) code groups
simultaneously on all four lanes (denoted as ||R|| column) during inter-packet
gaps, adhering to rules listed in the IEEE P802.3ae specification.
The rate match operation begins after rx_syncstatus and rx_channelaligned are
asserted. The rx_syncstatus signal is from the word aligner, indicating that
synchronization is acquired on all four channels, while rx_channelaligned signal is
from the deskew FIFO, indicating channel alignment.
The rate match FIFO looks for the ||R|| column (simultaneous /R/ code groups on
all four channels) and deletes or inserts ||R|| columns to prevent the rate match
FIFO from overflowing or under running. The rate match FIFO can insert or delete as
many ||R|| columns as necessary to perform the rate match operation.
The rx_rmfifodatadeleted and rx_rmfifodatainserted flags that indicate rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the
four channels goes high for one clock cycle per deleted ||R|| column. If an ||R||
column is inserted, the rx_rmfifoinserted flag from each of the four channels goes
high for one clock cycle per inserted ||R|| column.
1 The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively. You must then assert
the rx_digitalreset signal to reset the receiver PCS blocks.
Deterministic Latency Mode
Deterministic Latency mode provides the transceiver configuration that allows no
latency uncertainty in the datapath and features to strictly control latency variation.
This mode supports non-bonded (×1) and bonded (×4) channel configurations, and is
typically used to support CPRI and OBSAI protocols that require accurate delay
measurements along the datapath. The Cyclone IV GX transceivers configured in
Deterministic Latency mode provides the following features:
■ registered mode phase compensation FIFO
■ receive bit-slip indication
■ transmit bit-slip control
■ PLL PFD feedback
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2