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EP4CE30F29C7N Datasheet, PDF (157/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1 | |||
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Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support
7â11
Figure 7â6 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
banks of the Cyclone IV E device in the 144-pin EQFP and 164-pin MBGA packages.
Figure 7â6. DQS, CQ, or CQ# Pins for Cyclone IV E Devices in the 144-Pin EQFP and 164-pin
MBGA Packages
DQS0L/CQ1L
DQS1L/CQ1L#
I/O Bank 8
I/O Bank 7
Cyclone IV E Devices
in 144-pin EQFP and
164-pin MBGA
I/O Bank 3
I/O Bank 4
DQS0R/CQ1R
DQS1R/CQ1R#
In Cyclone IV devices, the Ã9 mode uses the same DQ and DQS pins as the Ã8 mode, and
one additional DQ pin that serves as a regular I/O pin in the Ã8 mode. The Ã18 mode
uses the same DQ and DQS pins as Ã16 mode, with two additional DQ pins that serve as
regular I/O pins in the Ã16 mode. Similarly, the Ã36 mode uses the same DQ and DQS
pins as the Ã32 mode, with four additional DQ pins that serve as regular I/O pins in
the Ã32 mode. When not used as DQ or DQS pins, the memory interface pins are
available as regular I/O pins.
Optional Parity, DM, and Error Correction Coding Pins
Cyclone IV devices support parity in Ã9, Ã18, and Ã36 modes. One parity bit is
available per eight bits of data pins. You can use any of the DQ pins for parity in
Cyclone IV devices because the parity pins are treated and configured similarly to DQ
pins.
DM pins are only required when writing to DDR2 and DDR SDRAM devices.
QDR II SRAM devices use the BWS# signal to select the byte to be written into
memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the
DM or BWS# pin high causes the memory to mask the DQ signals. Each group of DQS
and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are
clocked by the -90° shifted clock.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1
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